Wireless communication devices, such as mobile phone handsets, require a very high level of integration of hardware and firmware/software in order to achieve the necessary density of functionality, i.e. to realise the necessary functionality in a minimum device volume and at a minimum cost. An optimal wireless communication device design must also minimise power consumption in order to increase the battery call time and/or stand-by time.
Wireless communication devices also incorporate a number of distinct and operably coupled sub-systems, in order to provide the wide variety of functions and operations that a complex wireless communication device needs to perform. Such sub-systems comprise radio frequency power amplification functions, radio frequency integrated circuits (RFIC) comprising radio frequency generation, amplification, filtering, etc. functions, baseband integrated circuits (BBIC) comprising audio circuits, encoding/decoding, (de)modulation functions, processing functions, etc. and memory units.
Interfaces, which are often standardised to allow commonality and increased functionality between different chip-set manufacturers and different handset manufacturers, are defined for communicating between the respective sub-systems.
One typical interface found in a wireless communication device is the interface between a baseband integrated circuit (BBIC) and a radio frequency integrated circuit RFIC). Pins on ICs are used to route electrical signals between devices/elements/functions. It is generally desirable to minimise the number of pins in ICs used in wireless communication devices, as the use of extra pins, for example on a BBIC-RFIC interface, increases IC area, increases IC cost and complexity and increases power consumption.
In the field of mobile phones, a consortium of mobile phone manufacturers has been formed to define various sub-system interfaces, particularly interfaces between variants of second generation of cellular phones (2.xG) when migrating to cover additional, future wireless communication technologies, such as multimode transceivers additionally employing third generation (3G wideband code division multiple access (WCDMA) technology. This consortium is known as ‘DigRF’, and details of the defined interfaces and functionality thereof, particularly in a multimode mobile phone scenario, can be obtained from the DigRF consortium. It is noteworthy that Multimode operational specifications are not yet available at the time of filing this patent application.
One interface being defined by the DigRF consortium is the BB-RF interface standard, which encompasses a serial data interface for Receive (Rx) and Transmit (Tx) variants of second generation of cellular phones (2.xG) chipsets. When defining the interface to also accommodate the increased complexity and data rate required for 3G technology, it is clearly advantageous to minimise the IC pin count.
Furthermore, the standardised RFIC-BBIC interface for the current 2.xG mobile phone products does not provide for simultaneous Rx and TX data transfer to the RFIC. Although, providing such a simplex operation is acceptable in a 2G environment and 2G variants thereof, the corresponding limited bandwidth is not sufficient for 3G Rx or Tx operation.
Additionally, the standardised system clock frequency used in 2G mobile phones (SysClk) is defined as 26 Mhz. This frequency sets a useful data rate for 2.xG modes of operation. For 3G operation, it is not as useful as it is not an integer multiple of the WBCDMA chip rate.
The inventors of the present invention have recognised and appreciated that a further problem exists with running data interfaces oil such a radio transceiver system (say between the RFIC and the BBIC) in that to generate and decode random data patterns a clock source is required at the data rate, or an integer multiple thereof. This clock source is uniform and therefore the harmonic content of the clock source will not be spread.
Thus, a significant problem in the field of wireless communication devices is that the harmonic content power of clocks are known to radiate signals at frequencies that coincide with transmit and receive signals of the transceiver.
Notably, the ‘DigRF’ 2G standard for use in global system for Mobile telecommunications (GSM) standard mobile terminals has adopted a system clock rate of 26 MHz on the data interface between the baseband integrated circuit (IC) and the radio frequency (RF) IC. Notably, the use of such a defined clock rate creates fourteen harmonics in the GSM quad-band Rx and Tx frequency bands, i.e. the four frequency bands allocated for GSM in various regions of the world. This harmonic content problem generated by the clock signals running at 26 MHz requires radio transceiver designers to use slew rate control clocks to limit this problem.
Furthermore, very careful layout of the printed circuit board for the ICs used in the device is then required, to minimise the effect of these harmonics. Thus, the selection of a particular clock rate has a significant impact on the corresponding circuitry designed into the wireless communication device.
U.S. patent—U.S. Pat. No. 6,737,904 B1—of Philips Electronics N.V. discloses a 2G phone BBIC that aims to address the problems associated with the GSM 26 MHz system clock. U.S. Pat. No. 6,737,904 B1 discloses a mechanism of dynamically applying a random number generator to a 26 MHz clock signal to introduce jitter, and therefore introduce phase changes to the clock signal in order to spread noise.
A further solution to harmonic interference (purely and notably in a 2G environment) has been proposed in WO2002056488A2, inventor of Tuttle et. al. and titled Digital Interface Apparatus and Associated methods. In WO2002056488A2 suppression of interference between 2G ICs is performed using band limiting single-ended circuits and differential signals and an optimum die partition within the RF sub-system.
A further solution to harmonic interference, in the context of liquid crystal displays, is proposed in U.S. Pat. No. 6,720,943 B1, inventor Kim et. al. and titled Data Interface device. U.S. Pat. No. 6,720,943 B1 proposes to spread the electro-magnetic interference (EMI) by means of a clock dithering mechanism.
A problem associated with the clock dithering mechanism proposed in U.S. Pat. No. 6,720,943 B1 is that clock dithering spreads the noise but reduces the reliability of the data link. The use of a clock dithering mechanism creates a further problem in that there is increased hardware overhead. Dither needs to be random so as not to generate new tones. Thus, this technique attempts to reduce the contribution of harmonic noise to an RE sub-system, but fails to minimise or eliminate the harmonic noise.
Thus, existing solutions to clock harmonics attempt to ‘reduce’ the impact of the harmonic, predominantly by dithering the clock signal to spread the noise. A need therefore exists for a mechanism to incorporate integrated circuits/sub-systems and a corresponding data interface, within a wireless communications device, without incurring increased cost or complexity or increased pin count whilst minimising or eliminating the effects of harmonic interference of the clock signal(s).